TTL/H/L SERIES, 4-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16
TTL/H/L SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, PDIP14, DIP-14
AND-Gated J-K Positive-Edge-Triggered Flip-Flop with Peset and Clear 14-PDIP 0 to 70
IC TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, FF/Latch
Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear 16-PDIP 0 to 70