DDR2 SDRAM memory chip, 1Gbit density, organized as 128Mx8 with an 8-bit data bus width. Features a maximum clock rate of 533 MHz and 8 internal banks with 16M words per bank. Packaged in a 60-pin FBGA (Fine Pitch Ball Grid Array) with a 0.8mm pin pitch, suitable for surface mounting. Operates at a typical supply voltage of 1.8V, with a maximum access time of 0.5 ns.
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| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 60 |
| PCB | 60 |
| Package Length (mm) | 11.4 |
| Package Width (mm) | 8 |
| Package Height (mm) | 0.76 |
| Seated Plane Height (mm) | 1.1 |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 1Gbit |
| Type | DDR2 SDRAM |
| Organization | 128Mx8 |
| Data Bus Width | 8bit |
| Maximum Clock Rate | 533MHz |
| Number of Internal Banks | 8 |
| Number of Words per Bank | 16M |
| Maximum Access Time | 0.5ns |
| Density in Bits | 1073741824bit |
| Address Bus Width | 17bit |
| Typical Operating Supply Voltage | 1.8V |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Supply Voltage | 1.7V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 95°C |
| Cage Code | 9162F |
| EU RoHS | Yes |
| HTS Code | 8542320032 |
| Schedule B | 8542320015 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
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