1Gbit DDR2 SDRAM memory chip, organized as 128Mx8, featuring an 8-bit data bus width and a maximum clock rate of 400 MHz. This surface-mount component utilizes a 60-pin Fine Pitch Ball Grid Array (FBGA) package with a 0.8mm pin pitch. Operating at a typical supply voltage of 1.8V, it offers 8 internal banks and a maximum access time of 0.6 ns. The component is housed in a plastic package measuring 11.4mm x 8mm x 0.76mm.
PackageFBGA
MountingSurface Mount
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Technical Specifications
SK Hynix H5PS1G83EFR-E3L technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
60
PCB
60
Package Length (mm)
11.4
Package Width (mm)
8
Package Height (mm)
0.76
Pin Pitch (mm)
0.8
Package Material
Plastic
Mounting
Surface Mount
Density
1Gbit
Type
DDR2 SDRAM
Organization
128Mx8
Data Bus Width
8bit
Maximum Clock Rate
400MHz
Number of Internal Banks
8
Number of Words per Bank
16M
Maximum Access Time
0.6ns
Density in Bits
1073741824bit
Address Bus Width
17bit
Maximum Operating Current
100mA
Typical Operating Supply Voltage
1.8V
Max Operating Supply Voltage
1.9V
Min Operating Supply Voltage
1.7V
Min Operating Temperature
0°C
Max Operating Temperature
95°C
Compliance
Cage Code
9162F
EU RoHS
Yes
HTS Code
8542320032
Schedule B
8542320015
ECCN
EAR99
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2002/95/EC
Datasheet
SK Hynix H5PS1G83EFR-E3L Datasheet
Download the complete datasheet for SK Hynix H5PS1G83EFR-E3L to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.