DDR3 SDRAM memory chip with 1Gbit density, organized as 256Mx4, featuring a 4-bit data bus width and a maximum clock rate of 1066 MHz. This surface mount component utilizes a 78-pin Fine Pitch Ball Grid Array (FBGA) package with dimensions of 11mm x 7.5mm x 0.76mm. It operates at a typical supply voltage of 1.5V, with an 8-bank internal architecture and 32M words per bank. The operating temperature range is 0°C to 85°C.
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| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 78 |
| PCB | 78 |
| Package Length (mm) | 11 |
| Package Width (mm) | 7.5 |
| Package Height (mm) | 0.76 |
| Seated Plane Height (mm) | 1.1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 1Gbit |
| Type | DDR3 SDRAM |
| Organization | 256Mx4 |
| Data Bus Width | 4bit |
| Maximum Clock Rate | 1066MHz |
| Number of Internal Banks | 8 |
| Number of Words per Bank | 32M |
| Density in Bits | 1073741824bit |
| Address Bus Width | 17bit |
| Maximum Operating Current | 85mA |
| Typical Operating Supply Voltage | 1.5V |
| Max Operating Supply Voltage | 1.575V |
| Min Operating Supply Voltage | 1.425V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Cage Code | 9162F |
| EU RoHS | Yes |
| HTS Code | 8542320032 |
| Schedule B | 8542320015 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
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