DDR3L SDRAM memory chip offering 2 Gbit density with a 512Mx4 organization. Features a 4-bit data bus width and a maximum clock rate of 1600 MHz. Operates at a typical supply voltage of 1.35V and is housed in an 82-pin FBGA surface-mount package. Includes 8 internal banks and a maximum access time of 20 ns.
PackageFBGA
MountingSurface Mount
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Technical Specifications
SK Hynix H5TC2G43BFR-PBA technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 82 |
| PCB | 82 |
| Package Length (mm) | 11 |
| Package Width (mm) | 9.4 |
| Package Height (mm) | 0.76 |
| Seated Plane Height (mm) | 1.1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 2Gbit |
| Type | DDR3L SDRAM |
| Organization | 512Mx4 |
| Data Bus Width | 4bit |
| Maximum Clock Rate | 1600MHz |
| Number of Internal Banks | 8 |
| Number of Words per Bank | 64M |
| Maximum Access Time | 20ns |
| Density in Bits | 2147483648bit |
| Address Bus Width | 18bit |
| Maximum Operating Current | 105mA |
| Typical Operating Supply Voltage | 1.35V |
| Max Operating Supply Voltage | 1.45V |
| Min Operating Supply Voltage | 1.283V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
Compliance
| Cage Code | 9162F |
| EU RoHS | Yes |
| HTS Code | 8542320036 |
| Schedule B | 8542320023 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
SK Hynix H5TC2G43BFR-PBA Datasheet
Download the complete datasheet for SK Hynix H5TC2G43BFR-PBA to view detailed technical specifications.
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