2Gbit DDR3 SDRAM memory chip, organized as 512Mx4, featuring a 4-bit data bus width and an 18-bit address bus. Operates at a maximum clock rate of 1866 MHz with a typical supply voltage of 1.5V. Housed in an 82-pin FBGA package with a 0.8mm pin pitch, measuring 11.1mm x 9.4mm x 0.76mm. Supports 8 internal banks, each with 64M words, and operates within a temperature range of 0°C to 85°C. Surface mountable with a plastic package material.
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| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 82 |
| PCB | 82 |
| Package Length (mm) | 11.1 |
| Package Width (mm) | 9.4 |
| Package Height (mm) | 0.76 |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 2Gbit |
| Type | DDR3 SDRAM |
| Organization | 512Mx4 |
| Data Bus Width | 4bit |
| Maximum Clock Rate | 1866MHz |
| Number of Internal Banks | 8 |
| Number of Words per Bank | 64M |
| Density in Bits | 2147483648bit |
| Address Bus Width | 18bit |
| Typical Operating Supply Voltage | 1.5V |
| Max Operating Supply Voltage | 1.575V |
| Min Operating Supply Voltage | 1.425V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Cage Code | 9162F |
| EU RoHS | Yes |
| HTS Code | 8542320036 |
| Schedule B | 8542320023 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
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