2Gbit DDR3 SDRAM memory chip, organized as 128Mx16, featuring a 16-bit data bus width and a maximum clock rate of 1866 MHz. This surface-mount component utilizes a 96-pin Fine Pitch Ball Grid Array (FBGA) package with a 0.8mm pin pitch and dimensions of 13mm x 9mm x 0.76mm. Operating at a typical supply voltage of 1.5V, it offers 8 internal banks with 16M words per bank and a maximum access time of 20 ns.
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| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 96 |
| PCB | 96 |
| Package Length (mm) | 13 |
| Package Width (mm) | 9 |
| Package Height (mm) | 0.76 |
| Seated Plane Height (mm) | 1.1 |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 2Gbit |
| Type | DDR3 SDRAM |
| Organization | 128Mx16 |
| Data Bus Width | 16bit |
| Maximum Clock Rate | 1866MHz |
| Number of Internal Banks | 8 |
| Number of Words per Bank | 16M |
| Maximum Access Time | 20ns |
| Density in Bits | 2147483648bit |
| Address Bus Width | 17bit |
| Maximum Operating Current | 180mA |
| Typical Operating Supply Voltage | 1.5V |
| Max Operating Supply Voltage | 1.575V |
| Min Operating Supply Voltage | 1.425V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Cage Code | 9162F |
| EU RoHS | Yes |
| HTS Code | 8542320036 |
| Schedule B | 8542320023 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
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