High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger 16-CDIP -55 to 125
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| Package/Case | CDIP |
| Clock Edge Trigger Type | Negative Edge |
| Contact Plating | Tin, Lead |
| Frequency | 60MHz |
| High Level Output Current | -4mA |
| Lead Free | Contains Lead |
| Logic Function | JK-Type |
| Low Level Output Current | 4mA |
| Max Operating Temperature | 125°C |
| Min Operating Temperature | -55°C |
| Max Supply Voltage | 5.5V |
| Min Supply Voltage | 4.5V |
| Mount | Through Hole |
| Number of Bits | 2 |
| Number of Elements | 2 |
| Operating Supply Voltage | 5V |
| Packaging | Rail/Tube |
| Polarity | Non-Inverting |
| Propagation Delay | 56ns |
| Quiescent Current | 4uA |
| RoHS Compliant | No |
| Technology | CMOS |
| RoHS | Not Compliant |
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