CD74HC107EE4

Dual JK Flip-Flop, CMOS, Negative Edge Triggered, 35MHz, 2 Circuits

Dual negative-edge-triggered J-K flip-flops with reset, operating at up to 35MHz. This CMOS logic IC features two independent J-K flip-flop circuits, each with a single-ended input and non-inverting output. Designed for through-hole mounting in a 14-PDIP package, it offers a supply voltage range of 2V to 6V and a wide operating temperature range from -55°C to 125°C. Key specifications include a propagation delay of 170ns and a turn-on delay time of 14ns, with output currents of ±5.2mA.

Frequency35MHz

PackagePDIP

MountingThrough Hole

PolarityNon-Inverting

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Technical Specifications

Texas Instruments CD74HC107EE4 technical specifications.

General

Package/Case	PDIP
Clock Edge Trigger Type	Negative Edge
Contact Plating	Gold
Frequency	35MHz
High Level Output Current	-5.2mA
Input Type	SINGLE-ENDED
Lead Free	Lead Free
Logic Function	Flip-Flop, JK-Type
Low Level Output Current	5.2mA
Max Operating Temperature	125°C
Min Operating Temperature	-55°C
Max Supply Voltage	6V
Min Supply Voltage	2V
Mount	Through Hole
Number of Bits	2
Number of Bits per Element	1
Number of Circuits	2
Number of Elements	2
Number of Input Lines	2
Number of Output Lines	1
Output Current	5.2mA
Package Quantity	25
Packaging	Rail/Tube
Polarity	Non-Inverting
Propagation Delay	170ns
Quiescent Current	4uA
RoHS Compliant	Yes
Series	74HC
Technology	CMOS
Turn-On Delay Time	14ns
Weight	0.032734oz