CDC2509APWRG4

3.3-V Phase-Lock Loop (PLL) Clock Driver, featuring 9 3-state outputs and a maximum frequency of 100MHz. This surface-mount integrated circuit operates within a supply voltage range of 3V to 3.6V, with a typical operating voltage of 3.3V. Designed for clock buffering and driving applications, it offers LVTTL input compatibility and is housed in a 24-TSSOP package with gold contact plating. The component is RoHS compliant and operates across a temperature range of 0°C to 70°C.