32-bit ARM Cortex M3 RISC microcontroller featuring 64KB Flash program memory and 24KB RAM. This surface-mount device operates at up to 25 MHz, offering 67 programmable I/Os and multiple interfaces including I2C, SPI, SSI, and UART. Housed in a 64-pin LQFP package with a 0.5mm pitch, it supports dual ADCs with 16 channels each and operates within a voltage range of 1.32V to 3.6V, with an extended temperature range of -40°C to 85°C.
PackageLQFP
MountingSurface Mount
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Technical Specifications
Texas Instruments LM3S5P51-IQR25-C0T technical specifications.
General
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | QFP |
| Package/Case | LQFP |
| Package Description | Low Profile Quad Flat Package |
| Lead Shape | Gull-wing |
| Pin Count | 64 |
| PCB | 64 |
| Package Length (mm) | 10.2(Max) |
| Package Width (mm) | 10.2(Max) |
| Package Height (mm) | 1.45(Max) |
| Seated Plane Height (mm) | 1.6(Max) |
| Pin Pitch (mm) | 0.5 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-026BCD |
| Family Name | Stellaris |
| Data Bus Width | 32bit |
| Instruction Set Architecture | RISC |
| Maximum Clock Rate | 25MHz |
| Maximum CPU Frequency | 25MHz |
| Device Core | ARM Cortex M3 |
| Program Memory Type | Flash |
| Program Memory Size | 64KB |
| RAM Size | 24KB |
| Number of Programmable I/Os | 67 |
| Core Architecture | ARM |
| Programmability | Yes |
| Number of Timers | 4 |
| Interface Type | I2C/SPI/SSI/UART |
| Max Operating Supply Voltage | 1.32|3.6V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
| ADC Channels | 16/16 |
| Number of ADCs | Dual |
Compliance
| Cage Code | 01295 |
| HTS Code | 8542310001 |
| Schedule B | 8542310000 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU |
Datasheet
Texas Instruments LM3S5P51-IQR25-C0T Datasheet
Download the complete datasheet for Texas Instruments LM3S5P51-IQR25-C0T to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.