AND-Gated J-K Master-Slave Flip-Flop with Preset and Clear 14-PDIP 0 to 70
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Texas Instruments SN7472N technical specifications.
| Max Operating Temperature | 70 |
| Number of Terminals | 14 |
| Min Operating Temperature | 0 |
| Terminal Position | DUAL |
| JEDEC Package Code | R-PDIP-T14 |
| Width | 7.62 |
| Length | 19.305 |
| Pin Count | 14 |
| Number of Functions | 1 |
| Temperature Grade | COMMERCIAL |
| Supply Voltage-Nom (Vsup) | 5 |
| Supply Voltage-Max (Vsup) | 5.25 |
| Supply Voltage-Min (Vsup) | 4.75 |
| Logic IC Type | J-K FLIP-FLOP |
| Family | TTL/H/L |
| Propagation Delay (tpd) | 40 |
| Number of Bits | 2 |
| Load Capacitance | 15 |
| Output Polarity | COMPLEMENTARY |
| Power Supply Current-Max (ICC) | 20 |
| Trigger Type | NEGATIVE EDGE |
| fmax-Min | 15 |
| RoHS | No |
| Lead Free | No |
| HTS Code | 8542.39.00.01 |
| REACH | not_compliant |
| Military Spec | False |
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