JESD204B FPGA/IP Core Evaluation Board featuring 2GB RAM and a maximum clock frequency of 100 MHz. This evaluation board supports JESD204B technology for FPGA/IP core development. It includes 1 USB port, HSDC Pro IDE compatibility, and operates on Windows. Enhanced prototyping capabilities are provided with 22 LEDs and 7 push buttons/switches, along with JTAG support.
Texas Instruments TSW14J57EVM technical specifications.
| Type | Evaluation Board |
| Supported Device | JESD204B |
| Supported Device Technology | FPGA/IP Core |
| Maximum Clock Frequency | 100MHz |
| RAM Size | 2GB |
| USB | 1 |
| IDE | HSDC Pro |
| Windows | Win |
| Operating Systems | Win |
| JTAG Support | Yes |
| Number of LEDs | 22 |
| Push Buttons and Switches | 7 |
| RoHS | Not Required |
| RoHS Version | 2011/65/EU, 2015/863 |
No datasheet is available for this part.
