N-channel enhancement mode power MOSFET featuring 900V drain-source voltage and 9A continuous drain current. This single element silicon transistor utilizes pi-MOS II.5 process technology and is housed in a TO-3PN package with 3 pins and a tab, designed for through-hole mounting. Key specifications include a maximum gate-source voltage of ±30V, a typical gate charge of 120nC at 10V, and a maximum power dissipation of 150W. Operating temperature range is from -55°C to 150°C.
PackageTO-3PN
MountingThrough Hole
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Technical Specifications
Toshiba 2SK1358(PAIRTABCH) technical specifications.
General
| Basic Package Type | Through Hole |
| Package Family Name | TO-3PN |
| Package/Case | TO-3PN |
| Package Description | Transistor Outline Package |
| Lead Shape | Through Hole |
| Pin Count | 3 |
| PCB | 3 |
| Tab | Tab |
| Package Length (mm) | 15.9(Max) |
| Package Width (mm) | 4.5 |
| Package Height (mm) | 19 |
| Seated Plane Height (mm) | 22 |
| Pin Pitch (mm) | 5.45 |
| Package Material | Plastic |
| Mounting | Through Hole |
| Configuration | Single |
| Category | Power MOSFET |
| Channel Mode | Enhancement |
| Channel Type | N |
| Number of Elements per Chip | 1 |
| Process Technology | pi-MOS II.5 |
| Maximum Drain Source Voltage | 900V |
| Maximum Gate Source Voltage | ±30V |
| Maximum Continuous Drain Current | 9A |
| Material | Si |
| Maximum Gate Threshold Voltage | 3.5V |
| Maximum Drain Source Resistance | 1400@10VmOhm |
| Typical Gate Charge @ Vgs | 120@10VnC |
| Typical Gate Charge @ 10V | 120nC |
| Typical Input Capacitance @ Vds | 1300@25VpF |
| Maximum Power Dissipation | 150000mW |
| Min Operating Temperature | -55°C |
| Max Operating Temperature | 150°C |
Compliance
| Cage Code | S0562 |
| HTS Code | 8541290095 |
| Schedule B | 8541290080 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
Datasheet
Toshiba 2SK1358(PAIRTABCH) Datasheet
Download the complete datasheet for Toshiba 2SK1358(PAIRTABCH) to view detailed technical specifications.
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