P-channel enhancement mode power MOSFET featuring 20V drain-source voltage and 5A continuous drain current. This single-element silicon transistor utilizes U-MOS VI process technology and is housed in a compact 6-pin WCSP-C (BGA) package with a 0.5mm pin pitch. Key electrical characteristics include a maximum gate-source voltage of ±12V, a maximum drain-source on-resistance of 31mOhm at 8.5V, and a typical gate charge of 9.8nC at 4.5V. Designed for surface mounting, it offers a maximum power dissipation of 5000mW and operates across a wide temperature range from -55°C to 150°C.
PackageWCSP-C
MountingSurface Mount
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Technical Specifications
Toshiba SSM6J771G technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | WCSP-C |
| Lead Shape | Ball |
| Pin Count | 6 |
| PCB | 6 |
| Package Length (mm) | 1.5 |
| Package Width (mm) | 1 |
| Package Height (mm) | 0.3 |
| Seated Plane Height (mm) | 0.5 |
| Pin Pitch (mm) | 0.5 |
| Mounting | Surface Mount |
| Configuration | Single Dual Drain Triple Source |
| Category | Power MOSFET |
| Channel Mode | Enhancement |
| Channel Type | P |
| Number of Elements per Chip | 1 |
| Process Technology | U-MOS VI |
| Maximum Drain Source Voltage | 20V |
| Maximum Gate Source Voltage | ±12V |
| Maximum Continuous Drain Current | 5A |
| Material | Si |
| Maximum Gate Threshold Voltage | 1.2V |
| Maximum Drain Source Resistance | [email protected]mOhm |
| Typical Gate Charge @ Vgs | [email protected]nC |
| Typical Input Capacitance @ Vds | 870@10VpF |
| Maximum Power Dissipation | 5000mW |
| Min Operating Temperature | -55°C |
| Max Operating Temperature | 150°C |
Compliance
| Cage Code | S0562 |
| EU RoHS | Yes |
| HTS Code | 8541290095 |
| Schedule B | 8541290080 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Toshiba SSM6J771G Datasheet
Download the complete datasheet for Toshiba SSM6J771G to view detailed technical specifications.
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