CMOS 2-input NAND gate IC featuring four independent 2-input NAND elements. This integrated circuit utilizes CMOS technology for efficient operation. Housed in a 14-pin PDIP (Plastic Dual In Line Package) with through-hole mounting, it conforms to the MS-001AA JEDEC standard. Operating across a temperature range of -40°C to 85°C, this logic IC offers a 2.54mm pin pitch and a plastic package construction.
PackagePDIP
MountingThrough Hole
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Technical Specifications
Toshiba TC4011BP(N,M) technical specifications.
General
| Basic Package Type | Through Hole |
| Package Family Name | DIP |
| Package/Case | PDIP |
| Package Description | Plastic Dual In Line Package |
| Lead Shape | Through Hole |
| Pin Count | 14 |
| PCB | 14 |
| Package Length (mm) | 19.75(Max) |
| Package Width (mm) | 6.4 |
| Package Height (mm) | 3.5 |
| Seated Plane Height (mm) | 4.15 |
| Pin Pitch (mm) | 2.54 |
| Package Weight (g) | 0.96 |
| Package Material | Plastic |
| Mounting | Through Hole |
| Jedec | MS-001AA |
| Logic Family | 4000B |
| Logic Function | NAND |
| Process Technology | CMOS |
| Number of Elements per Chip | 4 |
| Number of Element Inputs | 2-IN |
| Number of Element Outputs | 1 |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
Compliance
| Cage Code | S0562 |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
Datasheet
Toshiba TC4011BP(N,M) Datasheet
Download the complete datasheet for Toshiba TC4011BP(N,M) to view detailed technical specifications.
No datasheet is available for this part.