Dual JK-Master-Slave Flip-Flop IC, featuring positive-edge triggering and CMOS logic. This integrated circuit offers two independent flip-flop elements, each with two inputs and one output, supporting inverting and non-inverting polarity. Housed in a 16-pin PDIP through-hole package with a 2.54mm pin pitch, it operates within a temperature range of -40°C to 85°C.
PackagePDIP
MountingThrough Hole
PolarityInverting/Non-Inverting
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Technical Specifications
Toshiba TC4027BP(N) technical specifications.
General
Basic Package Type
Through Hole
Package Family Name
DIP
Package/Case
PDIP
Package Description
Plastic Dual In Line Package
Lead Shape
Through Hole
Pin Count
16
PCB
16
Package Length (mm)
19.75(Max)
Package Width (mm)
6.4
Package Height (mm)
3.5
Seated Plane Height (mm)
4.15
Pin Pitch (mm)
2.54
Package Material
Plastic
Mounting
Through Hole
Jedec
MS-001BB
Logic Family
4000B
Logic Function
JK-Master-Slave Type
Process Technology
CMOS
Number of Elements per Chip
2
Number of Element Inputs
2
Number of Element Outputs
1
Polarity
Inverting/Non-Inverting
Triggering Type
Positive-Edge
Min Operating Temperature
-40°C
Max Operating Temperature
85°C
Compliance
Cage Code
S0562
EU RoHS
No
HTS Code
8542390001
Schedule B
8542390000
ECCN
EAR99
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Toshiba TC4027BP(N) Datasheet
Download the complete datasheet for Toshiba TC4027BP(N) to view detailed technical specifications.
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