CMOS D-Type transparent latch IC featuring 8 non-inverting inputs and 8 3-state outputs. This integrated circuit operates within a -40°C to 85°C temperature range and is housed in a 20-pin PDIP plastic dual in-line package with through-hole mounting. The package dimensions are 25.1mm (max) length, 6.4mm width, and 3.5mm height, with a 2.54mm pin pitch.
PackagePDIP
MountingThrough Hole
PolarityNon-Inverting
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Technical Specifications
Toshiba TC74HC573AP(HQ) technical specifications.
General
| Basic Package Type | Through Hole |
| Package Family Name | DIP |
| Package/Case | PDIP |
| Package Description | Plastic Dual In Line Package |
| Lead Shape | Through Hole |
| Pin Count | 20 |
| PCB | 20 |
| Package Length (mm) | 25.1(Max) |
| Package Width (mm) | 6.4 |
| Package Height (mm) | 3.5 |
| Pin Pitch (mm) | 2.54 |
| Package Material | Plastic |
| Mounting | Through Hole |
| Jedec | MS-001AD |
| Logic Family | HC |
| Process Technology | CMOS |
| Latch Mode | Transparent |
| Type | D-Type |
| Number of Elements per Chip | 1 |
| Number of Inputs per Chip | 8 |
| Number of Outputs per Chip | 8 |
| Output Type | 3-State |
| Polarity | Non-Inverting |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
Compliance
| Cage Code | S0562 |
| EU RoHS | No |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Toshiba TC74HC573AP(HQ) Datasheet
Download the complete datasheet for Toshiba TC74HC573AP(HQ) to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.