NPN Darlington transistor array featuring four elements per chip. Maximum collector-emitter voltage is 50V with a continuous DC collector current of 1.5A. Maximum power dissipation reaches 2700mW. This through-hole component is housed in a 16-pin PDIP package with a 2.54mm pin pitch. Operating temperature range is -40°C to 85°C.
PackagePDIP
MountingThrough Hole
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Technical Specifications
Toshiba TD62064AP(F,O,J,S) technical specifications.
General
Basic Package Type
Through Hole
Package Family Name
DIP
Package/Case
PDIP
Package Description
Plastic Dual In Line Package
Lead Shape
Through Hole
Pin Count
16
PCB
16
Package Length (mm)
19.75(Max)
Package Width (mm)
6.4
Package Height (mm)
3.5
Seated Plane Height (mm)
4.15
Pin Pitch (mm)
2.54
Package Material
Plastic
Mounting
Through Hole
Jedec
MS-001BB
Type
NPN
Configuration
Quad
Number of Elements per Chip
4
Maximum Collector-Emitter Voltage
50V
Maximum Continuous DC Collector Current
1.5A
Maximum Power Dissipation
2700mW
Maximum Collector-Emitter Saturation Voltage
Minimum DC Current Gain
800(Typ)@1A@2V|1500(Typ)@0.25A@2V
Min Operating Temperature
-40°C
Max Operating Temperature
85°C
Compliance
Cage Code
S0562
EU RoHS
Yes
Schedule B
8541290080
ECCN
EAR99
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2002/95/EC
Datasheet
Toshiba TD62064AP(F,O,J,S) Datasheet
Download the complete datasheet for Toshiba TD62064AP(F,O,J,S) to view detailed technical specifications.
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