Field Programmable Gate Array (FPGA) with 14,579 logic cells and 18,224 registers. Features 576 Kbit RAM, 64 (18x18) multipliers, and 32 dedicated DSP blocks. Supports up to 232 user I/Os and offers external memory interfaces for DDR, DDR2, DDR3, and LPDDR SDRAM. Operates on 1.2V with a 45nm process technology, providing transceiver speeds up to 3.2 Gbps. Packaged in a 324-pin Chip Scale Ball Grid Array (CSBGA) with a 0.8mm pin pitch, suitable for surface mounting.
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Xilinx XC6SLX16-3CSG324C technical specifications.
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | CSBGA |
| Package Description | Chip Scale Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 324 |
| PCB | 324 |
| Package Length (mm) | 15 |
| Package Width (mm) | 15 |
| Package Height (mm) | 0.9 |
| Seated Plane Height (mm) | 1.5(Max) |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Package Orientation | Yes |
| Package Orientation Marking Type | Dot |
| Jedec | MO-275KKAB-1 |
| Family Name | Spartan®-6 LX |
| Maximum Number of User I/Os | 232 |
| Number of Registers | 18224 |
| RAM Bits | 576Kbit |
| Device Logic Cells | 14579 |
| Process Technology | 45nm |
| Number of Multipliers | 64 (18x18) |
| Programmability | Yes |
| Transceiver Speed | 3.2Gbps |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Dedicated DSP | 32 |
| Speed Grade | 3 |
| External Memory Interface | DDR SDRAM|DDR2 SDRAM|DDR3 SDRAM|LPDDR SDRAM |
| Device Number of DLLs/PLLs | 6 |
| Total Number of Block RAM | 32 |
| Cage Code | 68994 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A991.d |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
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