
Field Programmable Gate Array (FPGA) with 24051 logic cells and 30064 registers, built on 45nm process technology. Features 936 Kbit RAM, 76 (18x18) multipliers, and 38 dedicated DSP blocks. Offers 6 DLLs/PLLs and 52 Block RAMs, supporting external memory interfaces including DDR, DDR2, DDR3, and LPDDR SDRAM. Operates at transceiver speeds up to 3.2 Gbps. Packaged in a 256-pin FTBGA (Fine Pitch Thin Ball Grid Array) with a 17mm x 17mm footprint, suitable for surface mounting.
Xilinx XC6SLX25-2FTG256C technical specifications.
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FTBGA |
| Package Description | Fine Pitch Thin Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 256 |
| PCB | 256 |
| Package Length (mm) | 17 |
| Package Width (mm) | 17 |
| Package Height (mm) | 1 |
| Seated Plane Height (mm) | 1.4 |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Package Orientation | Yes |
| Package Orientation Marking Type | Dot |
| Jedec | MS-034AAF-1 |
| Family Name | Spartan®-6 LX |
| Maximum Number of User I/Os | 186 |
| Number of Registers | 30064 |
| RAM Bits | 936Kbit |
| Device Logic Cells | 24051 |
| Process Technology | 45nm |
| Number of Multipliers | 76 (18x18) |
| Programmability | Yes |
| Transceiver Speed | 3.2Gbps |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Dedicated DSP | 38 |
| Speed Grade | 2 |
| External Memory Interface | DDR SDRAM|DDR2 SDRAM|DDR3 SDRAM|LPDDR SDRAM |
| Device Number of DLLs/PLLs | 6 |
| Total Number of Block RAM | 52 |
| Cage Code | 68994 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Download the complete datasheet for Xilinx XC6SLX25-2FTG256C to view detailed technical specifications.
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