Field Programmable Gate Array (FPGA) with 3840 logic cells and 4800 registers, built on 45nm process technology. Features 216 Kbit RAM, 12 block RAMs, and 16 integrated 18x18 multipliers, alongside 8 dedicated DSP blocks. Offers 576 maximum user I/Os and a transceiver speed of 3.2 Gbps. Packaged in a 900-pin, 31mm x 31mm x 1.75mm Fine Pitch Ball Grid Array (FBGA) for surface mounting. Operates across a temperature range of -40°C to 100°C.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Xilinx XC6SLX4-L1FGG900I technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 900 |
| PCB | 900 |
| Package Length (mm) | 31 |
| Package Width (mm) | 31 |
| Package Height (mm) | 1.75 |
| Seated Plane Height (mm) | 2.25 |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-034 |
| Family Name | Spartan®-6 LX |
| Maximum Number of User I/Os | 576 |
| Number of Registers | 4800 |
| RAM Bits | 216Kbit |
| Device Logic Cells | 3840 |
| Process Technology | 45nm |
| Number of Multipliers | 16 (18x18) |
| Programmability | Yes |
| Transceiver Speed | 3.2Gbps |
| Program Memory Type | SRAM |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 100°C |
| Dedicated DSP | 8 |
| Speed Grade | 1L |
| Device Number of DLLs/PLLs | 6 |
| Total Number of Block RAM | 12 |
Compliance
| Cage Code | 68994 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A991.d |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU |
Datasheet
Xilinx XC6SLX4-L1FGG900I Datasheet
Download the complete datasheet for Xilinx XC6SLX4-L1FGG900I to view detailed technical specifications.
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