Field Programmable Gate Array (FPGA) with 43661 logic cells and 54576 registers, built on 45nm process technology. Features 316 maximum user I/Os, 2088 Kbit RAM, 116 (18x18) multipliers, and 58 dedicated DSP blocks. Operates with a 3.2 Gbps transceiver speed and supports external memory interfaces including DDR, DDR2, DDR3, and LPDDR SDRAM. Packaged in a 484-pin Fine Pitch Ball Grid Array (FBGA) with a 1mm pin pitch, suitable for surface mounting and operating between -40°C and 100°C.
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Xilinx XC6SLX45-2FGG484I technical specifications.
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 484 |
| PCB | 484 |
| Package Length (mm) | 23 |
| Package Width (mm) | 23 |
| Package Height (mm) | 1.7 |
| Seated Plane Height (mm) | 2.2 |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Package Orientation | Yes |
| Package Orientation Marking Type | Dot |
| Jedec | MS-034AAJ-1 |
| Family Name | Spartan®-6 LX |
| Maximum Number of User I/Os | 316 |
| Number of Registers | 54576 |
| RAM Bits | 2088Kbit |
| Device Logic Cells | 43661 |
| Process Technology | 45nm |
| Number of Multipliers | 116 (18x18) |
| Programmability | Yes |
| Transceiver Speed | 3.2Gbps |
| Program Memory Type | SRAM |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 100°C |
| Dedicated DSP | 58 |
| Speed Grade | 2 |
| External Memory Interface | DDR SDRAM|DDR2 SDRAM|DDR3 SDRAM|LPDDR SDRAM |
| Device Number of DLLs/PLLs | 12 |
| Total Number of Block RAM | 116 |
| Cage Code | 68994 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A991.d |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
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