Field Programmable Gate Array (FPGA) with 43,661 logic cells and 54,576 registers, built on 45nm process technology. Features 2,088 Kbit RAM, 116 (18x18) multipliers, and 58 dedicated DSP blocks. Offers 106 maximum user I/Os and 12 DLLs/PLLs. Operates with a transceiver speed of 3.2 Gbps and utilizes SRAM for program memory. Packaged in a 196-pin Chip Scale Ball Grid Array (CSBGA) with a 0.5mm pin pitch, measuring 8x8x0.8mm, suitable for surface mounting.
PackageCSBGA
MountingSurface Mount
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Technical Specifications
Xilinx XC6SLX45-3CPG196I technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | CSBGA |
| Package Description | Chip Scale Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 196 |
| PCB | 196 |
| Package Length (mm) | 8 |
| Package Width (mm) | 8 |
| Package Height (mm) | 0.8 |
| Seated Plane Height (mm) | 1 |
| Pin Pitch (mm) | 0.5 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Family Name | Spartan®-6 LX |
| Maximum Number of User I/Os | 106 |
| Number of Registers | 54576 |
| RAM Bits | 2088Kbit |
| Device Logic Cells | 43661 |
| Process Technology | 45nm |
| Number of Multipliers | 116 (18x18) |
| Programmability | Yes |
| Transceiver Speed | 3.2Gbps |
| Program Memory Type | SRAM |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 100°C |
| Dedicated DSP | 58 |
| Speed Grade | 3 |
| Device Number of DLLs/PLLs | 12 |
| Total Number of Block RAM | 116 |
Compliance
| Cage Code | 68994 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU |
Datasheet
Xilinx XC6SLX45-3CPG196I Datasheet
Download the complete datasheet for Xilinx XC6SLX45-3CPG196I to view detailed technical specifications.
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