Field Programmable Gate Array (FPGA) featuring 4075 Configurable Logic Blocks (CLBs) and 52160 cells, operating at a maximum clock frequency of 1098MHz. This CMOS device utilizes a 236-pin PBGA package with terminals positioned at the bottom. It supports a nominal supply voltage of 1V, with a range from 0.95V to 1.05V, and offers 106 inputs and 106 outputs. The JEDEC package code is S-PBGA-B236, with a package width and length of 10.
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| Number of Terminals | 236 |
| Terminal Position | BOTTOM |
| JEDEC Package Code | S-PBGA-B236 |
| Width | 10 |
| Length | 10 |
| Pin Count | 236 |
| Supply Voltage-Nom | 1 |
| Supply Voltage-Min | 0.95 |
| Supply Voltage-Max | 1.05 |
| Number of Outputs | 106 |
| Clock Frequency-Max | 1098 |
| Number of Inputs | 106 |
| RoHS | Yes |
| Eccn Code | EAR99 |
| Lead Free | Yes |
| HTS Code | 8542.39.00.01 |
| REACH | Compliant |
| Military Spec | False |
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