GateMate A1 is a 28 nm FPGA for small to medium programmable-logic applications. It provides 20,480 configurable programmable elements, 1,280 Kb of block RAM, four PLLs, and one 5 Gb/s SerDes. The device supports 162 single-ended or 81 differential I/Os with 1.2 V to 2.5 V signaling, DDR support, and MIPI D-PHY compatibility. It operates across a -40 °C to +125 °C temperature range and is offered in a 324-ball 0.8 mm FBGA package or bare-die form.
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| Technology | 28nm |
| Logic cells | 20,480 CPE |
| 8-input LUT trees | 20,480 |
| 4-input LUT trees | 40,960 |
| Flip-flops/latches | 40,960 |
| Block RAM total | 1,280Kb |
| Block RAM organization | 64 x 20 Kb or 32 x 40 Kb |
| PLLs | 4 |
| PLL maximum frequency | 420MHz |
| SerDes channels | 1 |
| SerDes data rate | 5Gb/s |
| Single-ended I/O | 162 |
| Differential I/O | 81 |
| I/O voltage range | 1.2 to 2.5V |
| Core voltage modes | 0.9, 1.0, 1.1V |
| Leakage current | 12 at 1.0 V and 20 °CmA |
| Operating temperature range | -40 to +125°C |
| Package | 324-ball 0.8 mm FBGA, 15 mm x 15 mm |
| RoHS | RoHS 3 declaration available |
| REACH | REACH declaration available |
Download the complete datasheet for Cologne Chip CCGM1A1 to view detailed technical specifications.
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These are design resources that include the Cologne Chip CCGM1A1
Hardware design document for the Olimex GateMateA1-EVB, featuring the Cologne Chip CCGM1A1 FPGA and a Raspberry Pi RP2040 microcontroller for configuration.
Schematic and design document for the Olimex GateMateA1-EVB Rev B, featuring the Cologne Chip CCGM1A1 FPGA, RP2040 programmer, and TPS62A02 power management.
Hardware schematic for the GateMateA1-EVB, featuring the CCGM1A1 FPGA, RP2040 controller, and peripherals like VGA, PS/2, and Pmod interfaces.
Installation guide for the Cologne Chip GateMate FPGA toolchain, covering synthesis, implementation, and programming on Windows and Linux for CCGM1A1 devices.
