Skip to main content
Design DocumentRaw Githubusercontent

Olimex GateMateA1-EVB Rev.C FPGA Evaluation Board

Hardware schematic for the GateMateA1-EVB, featuring the CCGM1A1 FPGA, RP2040 controller, and peripherals like VGA, PS/2, and Pmod interfaces.

View design document

Overview

This design document provides the Rev.C hardware schematic for the GateMateA1-EVB evaluation board, centered on the Cologne Chip CCGM1A1 GateMate FPGA. The design incorporates a Raspberry Pi RP2040 for JTAG programming and system management. Power regulation is handled by Texas Instruments TPS62A02ADRLR buck converters to provide 1.2V core, 1.8V, and 2.5V rails. The board includes multiple interfaces including VGA, a PS/2 mini-DIN port, and Pmod headers using TXB0108PWR level shifters. Memory support is provided through Zetta Device SPI Flash and Lyontek SRAM.

Use Cases

  • FPGA prototyping and development
  • Hardware evaluation of Cologne Chip GateMate series
  • Reference design for RP2040-based JTAG controllers
  • Embedded system design with VGA and PS/2 peripherals

Topics

GateMateA1-EVB
CCGM1A1
FPGA
Olimex
RP2040
TPS62A02ADRLR
TXB0108PWR
VGA
PS/2
Pmod
Schematic

Referenced Parts

TXB0108PWR

Texas Instruments

U5 TXB0108PWR(TSSOP-20)

CCGM1A1

Cologne Chip

U1H CCGM1A1(FBGA-324)

HX7027

Hexin

U2 HX7027(SOT-23-3)

BSS138

Onsemi

FET2 BSS138(SOT-23-3)

RP2040

Raspberry Pi

U10 RP2040(QFN-56_7x7mm_P0.4mm)

TPS62A02ADRLR

Texas Instruments

U15 TPS62A02ADRLR(SOT-563-6)

PIM201610-1R0MTS00

Cyntec

L7 1.0uH/4.2A/DCR=35mR/20%/2.00x1.60x1.00mm/L2016(PIM201610-1R0MTS00)

DSHP04TS-S

Diptronics

CFG_SET1 DSHP04TS-S

SX5M10.000M20F30TNN

LCSC

CR1 Q10MHz/30ppm/1.62V-3.63V/4P/5x3.2mm(SX5M10.000M20F30TNN_LCSC-C2901522)

LY68S3200SLT

Lyontek

U7 LY68S3200SLT(SOIC-8_150mil)

ZD25WQ16CSIGT

Zetta Device

U8 ZD25WQ16CSIGT(SOIC-8_208mils)

GG0402052R542P

G-NOR

TVS5 NA(GG0402052R542P)

YTS-A016-X

Yite

FPGA_BUT1 YTS-A016-X

1N5819S4

Generic

D1 1N5819S4/SOD123

133MHz

Maxim

For example, they can generate a 48MHz clock which meets the frequency accuracy requirement of the USB interface and a 133MHz maximum speed system clock.

Olimex GateMateA1-EVB Rev.C FPGA Evaluation Board | Design Resources