125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface 48-WQFN -40 to 85
125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface 48-WQFN -40 to 85
125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface 48-WQFN -40 to 85
Dual UART I2C/SPI Bridge, 64-B FIFO, 3.125 Gbps, AEC-Q100, HVQCCN-48
125 to 312.5-MHz FPGA-link deserializer with DDR LVDS parallel interface 48-WQFN -40 to 85