The 24-bit digital signal processor provides a DSP56300-compatible core for networking, security encryption, and home entertainment applications. It delivers 275 MMACS at a 275 MHz internal clock and can reach 550 MMACS when the enhanced filter coprocessor is used. The device operates from a 1.6 V core supply with independent 3.3 V I/O and includes 192 K x 24-bit on-chip RAM plus a 192 x 24-bit bootstrap ROM. Integrated peripherals include a six-channel DMA controller, HI08 host interface, two ESSI ports, SCI, triple timer, JTAG, and OnCE debug support. The package is a 196-pin molded array plastic-ball grid array with lead-free and lead-bearing versions described in the datasheet.
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| Processor core | DSP56300 24-bit DSP |
| Maximum internal clock frequency | 275MHz |
| DSP performance | 275MMACS |
| DSP performance with EFCOP | 550MMACS |
| Core supply voltage | 1.5 to 1.7V |
| I/O supply voltage | 3.0 to 3.6V |
| On-chip RAM | 192 K x 24-bit total |
| Bootstrap ROM | 192 x 24-bit |
| Instruction cache | 1024 x 24-bit optional |
| DMA channels | 6 |
| Multiplier-accumulator | 24 x 24-bit MAC with 56-bit accumulators |
| Filter coprocessor | 24 x 24-bit EFCOP |
| Host interface | Enhanced 8-bit parallel HI08 |
| Synchronous serial interfaces | 2 ESSI ports |
| GPIO signals | Up to 34 |
| Operating junction temperature | -40 to 100°C |
| Package | 196-pin molded array plastic-ball grid array |
| Junction-to-case thermal resistance | 7°C/W |
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