Multimedia applications processor family integrates an ARM Cortex-A8 core with NEON, VFP, L1 caches, and a 256 KB L2 cache. The family supports up to 800 MHz consumer operation, DDR2 or mobile DDR memory clocks up to 200 MHz, and BGA package options in 13 x 13 mm or 19 x 19 mm sizes. Integrated multimedia blocks include 2D and 3D graphics acceleration, an image processing unit, a multi-standard video processing unit, display and camera interfaces, and TV output. Connectivity includes high-speed USB OTG plus host ports, 10/100 Ethernet, SD/MMC/SDIO, PATA, UART, I2C, SPI, I2S/SSI audio, SIM, GPIO, timers, and security accelerators.
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| Processor core | ARM Cortex-A8 r2p5 with TrustZone |
| Maximum ARM core frequency | 800MHz |
| L1 instruction cache | 32KB |
| L1 data cache | 32KB |
| L2 cache | 256KB |
| Internal RAM | 128KB |
| Boot ROM | 36KB |
| DDR memory clock | Up to 200MHz |
| Supported DRAM interfaces | 16/32-bit Mobile DDR and 16/32-bit DDR2 |
| 3D graphics performance | 27 Mtri/s, 166 Mpix/s |
| 2D graphics support | OpenVG 1.1, 166 Mpix/s |
| Video decode capability | H.264, MPEG-4, MPEG-2, VC-1 and other formats up to 720p at 30 fps |
| USB interfaces | High-speed USB OTG with on-chip PHY plus three high-speed host modules |
| Ethernet interface | 10/100Mbps |
| SD/MMC host controllers | Four eSDHC controllers, with eSDHC-4 muxed with PATA |
| Operating case temperature range | -40 to 95 industrial; -20 to 85 consumer°C |
| Package moisture sensitivity level | MSL 3 |
| RoHS | RoHS compliant, lead-free |
| Msl | 3 |
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These are design resources that include the Freescale Semiconductor i.MX51
Instructions for modifying the i.MX51 WinCE 6.0 BSP bootloader and kernel to support custom SDRAM hardware and timing parameters instead of the default EVK configuration.
Addendum providing corrections to the i.MX51 Reference Manual, including system memory map updates and High-Speed Communication (HSC) architecture details.
