The QUICC communication controller integrates a 32-bit CPU32+ processor core with communications and system-integration peripherals. It supports 0 MHz to 33 MHz static operation, up to a 32-bit external data bus, and 32 address lines. Seven serial channels are provided through four SCCs, two SMCs, and one SPI, with two TDM channels and a time-slot assigner for communications applications. The device also includes an eight-bank memory controller, four general-purpose timers, two independent DMA controllers, 14 serial DMA channels, 2.5 KB of dual-port RAM, and an IEEE 1149.1 test access port.
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| Processor core | CPU32+ |
| Core architecture | 32bit |
| Operating frequency | 0 to 33MHz |
| External data bus width | Up to 32 with dynamic 8- and 16-bit sizingbit |
| Address lines | 32 |
| Serial channels | 7 total |
| Serial communications controllers | 4 SCCs |
| Serial management controllers | 2 SMCs |
| Serial peripheral interface | 1 SPI |
| TDM channels | 2 |
| General-purpose timers | Four 16-bit timers or two 32-bit timers |
| Independent DMA controllers | 2 |
| Serial DMA channels | 14 |
| Dual-port RAM | 2.5KB |
| Memory controller banks | 8 |
| Test access port | IEEE 1149.1 JTAG |
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These are design resources that include the Freescale Semiconductor MC68360
Application note detailing how to interface SDRAM with the MC68360 QUICC processor using a CPLD to translate standard DRAM signals into JEDEC-compliant SDRAM commands.
Guidelines for connecting multiple MC145574 (S/T) or MC145572 (U) ISDN transceivers to a QUICC32 (MC68MH360) using QMC protocol and IDL2 TDM bus structures.
Describes a method to boot an MC68EC040/MC68360 system from a single 8-bit EPROM using the MC68360's IDMA and a PAL-based state machine to reduce costs and board space.
Application note detailing the glueless interface between the MC68360 QUICC communications controller and the MC68160 Ethernet serial interface adapter.
