512Mbit DDR SDRAM memory chip, organized as 32Mx16, featuring a 16-bit data bus width and a maximum clock rate of 133 MHz. This surface-mount component utilizes a 60-pin Thin Fine Pitch Ball Grid Array (TFBGA) package with a 0.8mm pin pitch. It operates at a typical supply voltage of 1.8V, with a density of 536,870,912 bits and four internal banks.
PackageTFBGA
MountingSurface Mount
Quick Jump:
Technical Specifications
Integrated Silicon Solution IS43LR16320B-75BL technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
TFBGA
Package Description
Thin Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
60
PCB
60
Package Length (mm)
10
Package Width (mm)
8
Package Height (mm)
0.7(Max)
Seated Plane Height (mm)
1.1(Max)
Pin Pitch (mm)
0.8
Package Material
Plastic
Mounting
Surface Mount
Density
512Mbit
Type
DDR SDRAM
Organization
32Mx16
Data Bus Width
16bit
Maximum Clock Rate
133MHz
Number of Internal Banks
4
Number of Words per Bank
8M
Maximum Access Time
8|6ns
Density in Bits
536870912bit
Address Bus Width
15bit
Maximum Operating Current
100mA
Typical Operating Supply Voltage
1.8V
Max Operating Supply Voltage
1.95V
Min Operating Supply Voltage
1.7V
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Compliance
Cage Code
1J9V2
EU RoHS
Yes
HTS Code
8542320028
Schedule B
8542320015
ECCN
EAR99
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Integrated Silicon Solution IS43LR16320B-75BL Datasheet
Download the complete datasheet for Integrated Silicon Solution IS43LR16320B-75BL to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.