Synchronous SRAM chip, 36M-bit density, organized as 2M x 18 bits. Features a 250 MHz maximum clock rate with DDR data rate architecture and pipelined operation. Housed in a 165-pin LFBGA package with a 1mm pin pitch, measuring 17mm x 15mm x 0.94mm. Operates from a 1.8V supply voltage (1.7V to 1.9V range) and supports surface mounting. Suitable for -40°C to 85°C operating temperatures.
PackageLFBGA
MountingSurface Mount
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Technical Specifications
Integrated Silicon Solution IS61DDB22M18-250M3LI technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
LFBGA
Package Description
Low Profile Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
17
Package Width (mm)
15
Package Height (mm)
0.94(Max)
Seated Plane Height (mm)
1.4(Max)
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Density
36Mbit
Address Bus Width
21bit
Timing Type
Synchronous
Maximum Clock Rate
250MHz
Data Rate Architecture
DDR
Density in Bits
37748736bit
Maximum Operating Current
550mA
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
18bit
Number of Ports
1
Number of Words
2M
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
-40°C
Max Operating Temperature
85°C
Architecture
Pipelined
Compliance
Cage Code
1J9V2
EU RoHS
Yes
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Integrated Silicon Solution IS61DDB22M18-250M3LI Datasheet
Download the complete datasheet for Integrated Silicon Solution IS61DDB22M18-250M3LI to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.