Field Programmable Gate Array (FPGA) with 340,000 logic cells and 513,000 registers, built on 28nm process technology. Features 1517 pins in a 40x40mm Flip Chip Fine Pitch Ball Grid Array (FC-FBGA) package for surface mounting. Offers 696 user I/Os, 19456 Kbit RAM, 512 (18x18) multipliers, 2 Ethernet MACs, 36 transceiver blocks operating at 14.1 Gbps, and 256 dedicated DSP blocks. Supports various external memory interfaces including DDR2/DDR3 SDRAM and RLDRAM. Operates within a 0°C to 85°C temperature range.
PackageFC-FBGA
MountingSurface Mount
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Technical Specifications
Intel 5SGXEA3K2F40C3N technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FC-FBGA |
| Package Description | Flip Chip Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 1517 |
| PCB | 1517 |
| Package Length (mm) | 40 |
| Package Width (mm) | 40 |
| Package Height (mm) | 2.7 |
| Seated Plane Height (mm) | 3.2 |
| Pin Pitch (mm) | 1 |
| Package Weight (g) | 15.2 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-034AAU-1 |
| Family Name | Stratix® V GX |
| Maximum Number of User I/Os | 696 |
| Number of Registers | 513000 |
| RAM Bits | 19456Kbit |
| Device Logic Cells | 340000 |
| Number of Look-up Table Input | 8 |
| Process Technology | 28nm |
| Ethernet MACs | 2 |
| Number of Multipliers | 512 (18x18) |
| Programmability | Yes |
| Transceiver Blocks | 36 |
| Transceiver Speed | 14.1Gbps |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Dedicated DSP | 256 |
| PCI Blocks | 2 |
| Speed Grade | 3 |
| Differential I/O Standards Supported | LVPECL|LVDS|HCSL |
| Single-Ended I/O Standards Supported | LVTTL|LVCMOS |
| External Memory Interface | DDR2 SDRAM|DDR3 SDRAM|RLDRAM II|RLDRAM III|QDRII+SRAM |
| Device Number of DLLs/PLLs | 20 |
| Supported IP Core | Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Sub-frame Latency JPEG 2000 Encoder (BA130)|SPAUI MAC|RLDRAM II Controller Core|RapidIO to AXI Bridge Controller (RAB)|RapidIO to AXI Bridge Controller (RAB) |
| Supported IP Core Manufacture | Altera/Barco Silex/Mobiveil, Inc |
| Total Number of Block RAM | 957 |
Compliance
| Cage Code | 4BA62 |
| EU RoHS | Yes with Exemption |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A001.a.7.b |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Intel 5SGXEA3K2F40C3N Datasheet
Download the complete datasheet for Intel 5SGXEA3K2F40C3N to view detailed technical specifications.
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