64-bit RISC microprocessor featuring a 32nm Sandy Bridge Xeon UP architecture. This 4-core processor operates at a maximum speed of 3400 MHz with a 32KB instruction cache and 32KB data cache. It utilizes a 1155-Pin LGA (Land Grid Array) surface mount package with a plastic construction, measuring 37.5mm x 37.5mm. Maximum operating supply voltage is 1.86V.
PackageLGA
MountingSurface Mount
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Technical Specifications
Intel CM8062307262003 SR00P technical specifications.
General
| Basic Package Type | Non-Lead-Frame SMT |
| Package Family Name | LGA |
| Package/Case | LGA |
| Package Description | Land Grid Array Package |
| Lead Shape | No Lead |
| Pin Count | 1155 |
| PCB | 1155 |
| Package Length (mm) | 37.5 |
| Package Width (mm) | 37.5 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Family Name | Sandy Bridge Xeon UP Processor E3-1275 Processor |
| Data Bus Width | 64bit |
| Instruction Set Architecture | RISC |
| Device Core | Xeon |
| Maximum Speed | 3400MHz |
| Process Technology | 32nm |
| Number of CPU Cores | 4 |
| Interface Type | DMI/PECI |
| CAN | 0 |
| UART | 0 |
| USART | 0 |
| I2C | 0 |
| SPI | 0 |
| USB | 0 |
| Ethernet | 0 |
| I2S | 0 |
| Max Operating Supply Voltage | 1.86V |
| Instruction Cache Size | 32KB |
| Data Cache Size | 32KB |
| Multiply Accumulate | No |
Compliance
| Cage Code | 4BA62 |
| EU RoHS | Yes |
| HTS Code | 8542310001 |
| Schedule B | 8542310000 |
| ECCN | 5A992.c |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2011/65/EU |
Datasheet
Intel CM8062307262003 SR00P Datasheet
Download the complete datasheet for Intel CM8062307262003 SR00P to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.