Field Programmable Gate Array (FPGA) with 10570 logic cells and 48 multipliers. Features 898.9 Kbit RAM, 6 dedicated DSP blocks, and 30 SERDES channels. Supports various external memory interfaces including DDR SDRAM and QDR II+ SRAM. Operates within a 0 °C to 85 °C temperature range. Packaged in a 780-pin FC-FBGA (Flip Chip Fine Pitch Ball Grid Array) for surface mounting.
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| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FC-FBGA |
| Package Description | Flip Chip Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 780 |
| PCB | 780 |
| Package Length (mm) | 29 |
| Package Width (mm) | 29 |
| Package Height (mm) | 3(Max) |
| Seated Plane Height (mm) | 3.5(Max) |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-034AAM-1 |
| Family Name | Stratix® |
| Maximum Number of User I/Os | 426 |
| RAM Bits | 898.9Kbit |
| Device Logic Cells | 10570 |
| Process Technology | 130nm |
| Number of Multipliers | 48 (9x9) |
| Programmability | No |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Dedicated DSP | 6 |
| Maximum Number of SERDES Channels | 30 |
| Speed Grade | 7 |
| Differential I/O Standards Supported | LVPECL|LVDS|PCML |
| Single-Ended I/O Standards Supported | LVTTL|LVCMOS |
| External Memory Interface | DDR SDRAM|FCRAM|QDR II+SRAM|ZBT SRAM |
| Device Number of DLLs/PLLs | 6 |
| Supported IP Core | Video LVDS SerDes Transmitter / Receiver|PCI Express Cores|IFI Advanced CAN IP|DI2CSB I2C Bus Interface-Slave|32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz |
| Supported IP Core Manufacture | Microtronix Inc/CAST, Inc/Northwest Logic, Inc/IFI/Digital Core Design/PLDA |
| Total Number of Block RAM | 1+60+94 |
| Cage Code | 4BA62 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A991.d |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU |
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