EP20K100EFC324XNES

FPGA APEX 20K, 100K Gates, 4160 Cells, 324-Pin FBGA, 0.22um

Field Programmable Gate Array (FPGA) with 4160 logic cells and 263,000 system gates, built on 0.22um process technology. Features 52 Kbit RAM, 26 Block RAMs, and 2 DLLs/PLLs. Supports up to 246 user I/Os with differential standards including LVPECL, LVDS, PCI-X, AGP, CTT, and single-ended LVTTL, LVCMOS. Offers external memory interface for DDR SDRAM and ZBT SRAM. Packaged in a 324-pin Fine Pitch Ball Grid Array (FBGA) for surface mounting, operating from 0°C to 85°C.

PackageFBGA

MountingSurface Mount

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Technical Specifications

Intel EP20K100EFC324XNES technical specifications.

General

Basic Package Type	Ball Grid Array
Package Family Name	BGA
Package/Case	FBGA
Package Description	Fine Pitch Ball Grid Array
Lead Shape	Ball
Pin Count	324
PCB	324
Package Length (mm)	19
Package Width (mm)	19
Package Height (mm)	1.8(Max)
Seated Plane Height (mm)	2.2(Max)
Pin Pitch (mm)	1
Package Material	Plastic
Mounting	Surface Mount
Jedec	MS-034AAG-1
Family Name	APEX 20K
Maximum Number of User I/Os	246
RAM Bits	52Kbit
Device Logic Cells	4160
Process Technology	0.22um
Device System Gates	263000
Programmability	No
Program Memory Type	SRAM
Min Operating Temperature	0°C
Max Operating Temperature	85°C
Speed Grade	STD
Differential I/O Standards Supported	LVPECL\|LVDS\|PCI-X\|AGP\|CTT
Single-Ended I/O Standards Supported	LVTTL\|LVCMOS
External Memory Interface	DDR SDRAM\|ZBT SRAM
Device Number of DLLs/PLLs	2
Total Number of Block RAM	26

Compliance

Cage Code	4BA62
EU RoHS	Yes
HTS Code	8542390001
Schedule B	8542390000
ECCN	3A991.d
Automotive	No
AEC Qualified	No
PPAP	No
Radiation Hardening	No
RoHS Versions	2002/95/EC

Datasheet

This datasheet cannot be embedded due to technical restrictions.

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