Field Programmable Gate Array (FPGA) with 526,000 system gates and 8,320 logic cells. Features 104 Kbit RAM, 52 block RAMs, and 2 DLLs/PLLs. Supports up to 168 user I/Os with differential standards including LVPECL, LVDS, PCI-X, AGP, and CTT, alongside single-ended LVTTL and LVCMOS. Offers external memory interfaces for DDR SDRAM and ZBT SRAM. Packaged in a 240-pin PQFP (Plastic Quad Flat Package) with gull-wing leads for surface mounting, measuring 32x32mm with a 0.5mm pin pitch. Operates within a temperature range of 0°C to 85°C.
PackagePQFP
MountingSurface Mount
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Technical Specifications
Intel EP20K200EQC240NES technical specifications.
General
Basic Package Type
Lead-Frame SMT
Package Family Name
QFP
Package/Case
PQFP
Package Description
Plastic Quad Flat Package
Lead Shape
Gull-wing
Pin Count
240
PCB
240
Package Length (mm)
32
Package Width (mm)
32
Package Height (mm)
3.4
Seated Plane Height (mm)
4.1(Max)
Pin Pitch (mm)
0.5
Package Material
Plastic
Mounting
Surface Mount
Jedec
MS-029GA
Family Name
APEX 20K
Maximum Number of User I/Os
168
RAM Bits
104Kbit
Device Logic Cells
8320
Process Technology
0.22um
Device System Gates
526000
Programmability
No
Program Memory Type
SRAM
Min Operating Temperature
0°C
Max Operating Temperature
85°C
Speed Grade
STD
Differential I/O Standards Supported
LVPECL|LVDS|PCI-X|AGP|CTT
Single-Ended I/O Standards Supported
LVTTL|LVCMOS
External Memory Interface
DDR SDRAM|ZBT SRAM
Device Number of DLLs/PLLs
2
Total Number of Block RAM
52
Compliance
Cage Code
4BA62
EU RoHS
Yes
HTS Code
8542390001
Schedule B
8542390000
ECCN
EAR99
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU
Datasheet
Intel EP20K200EQC240NES Datasheet
Download the complete datasheet for Intel EP20K200EQC240NES to view detailed technical specifications.
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