Field Programmable Gate Array (FPGA) with 132,540 logic cells and 6589.7 Kbit RAM. Features 252 multipliers (18x18) and 63 dedicated DSP blocks. Utilizes 90nm process technology and supports a maximum of 1126 user I/Os. Operates with a 1.2V supply and is housed in a 1508-pin FC-FBGA package. Supports various external memory interfaces including DDR SDRAM and DDR2 SDRAM.
PackageFC-FBGA
MountingSurface Mount
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Technical Specifications
Intel EP2S130F1508C5NES technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FC-FBGA
Package Description
Flip Chip Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
1508
PCB
1508
Package Length (mm)
40
Package Width (mm)
40
Package Height (mm)
3(Max)
Seated Plane Height (mm)
3.5(Max)
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Jedec
MS-034AAU-1
Family Name
Stratix® II
Maximum Number of User I/Os
1126
RAM Bits
6589.7Kbit
Device Logic Cells
132540
Process Technology
90nm
Number of Multipliers
252 (18x18)
Programmability
No
Program Memory Type
SRAM
Min Operating Temperature
0°C
Max Operating Temperature
85°C
Dedicated DSP
63
Speed Grade
5
Differential I/O Standards Supported
LVPECL|LVDS
Single-Ended I/O Standards Supported
LVTTL|CMOS|SSTL|HSTL
External Memory Interface
DDR SDRAM|DDR2 SDRAM|RLDRAM II|QDRII+SRAM
Device Number of DLLs/PLLs
12
Supported IP Core
Viterbi Compiler, High-Speed Parallel Decoder|RapidIO to AXI Bridge Controller (RAB)|PowerPC/SH/1960 System Controller|32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz
Supported IP Core Manufacture
Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc/PLDA
Total Number of Block RAM
6+609+699
Compliance
Cage Code
4BA62
EU RoHS
Yes
HTS Code
8542390001
Schedule B
8542390000
ECCN
3A001.a.7.a
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU
Datasheet
Intel EP2S130F1508C5NES Datasheet
Download the complete datasheet for Intel EP2S130F1508C5NES to view detailed technical specifications.
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