Field-Programmable Gate Array (FPGA) with 179,400 logic cells and 1170 user I/Os. Features 9163.1 Kbit RAM, 384 multipliers (18x18), and 96 dedicated DSP blocks. Built on 90nm process technology, this device supports SRAM program memory and offers 12 DLLs/PLLs. It operates from 0°C to 85°C and is housed in a 1508-pin FC-FBGA package with a 1mm pin pitch for surface mounting.
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Intel EP2S180F1508C5NES technical specifications.
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FC-FBGA |
| Package Description | Flip Chip Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 1508 |
| PCB | 1508 |
| Package Length (mm) | 40 |
| Package Width (mm) | 40 |
| Package Height (mm) | 3(Max) |
| Seated Plane Height (mm) | 3.5(Max) |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-034AAU-1 |
| Family Name | Stratix® II |
| Maximum Number of User I/Os | 1170 |
| RAM Bits | 9163.1Kbit |
| Device Logic Cells | 179400 |
| Process Technology | 90nm |
| Number of Multipliers | 384 (18x18) |
| Programmability | No |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Dedicated DSP | 96 |
| Speed Grade | 5 |
| Differential I/O Standards Supported | LVPECL|LVDS |
| Single-Ended I/O Standards Supported | LVTTL|CMOS|SSTL|HSTL |
| External Memory Interface | DDR SDRAM|DDR2 SDRAM|RLDRAM II|QDRII+SRAM |
| Device Number of DLLs/PLLs | 12 |
| Supported IP Core | Viterbi Compiler, High-Speed Parallel Decoder|RapidIO to AXI Bridge Controller (RAB)|PowerPC/SH/1960 System Controller|32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz |
| Supported IP Core Manufacture | Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc/PLDA |
| Total Number of Block RAM | 9+768+930 |
| Cage Code | 4BA62 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A001.a.7.a |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU |
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