Field Programmable Gate Array (FPGA) with 60,440 logic cells and 144 dedicated 18x18 multipliers. Features 2484.6 Kbit of RAM, 36 dedicated DSP blocks, and 12 DLLs/PLLs. Operates on 1.2V with 90nm process technology, supporting up to 718 user I/Os. Packaged in a 1020-pin FC-FBGA (33x33mm) for surface mounting. Supports DDR SDRAM, DDR2 SDRAM, RLDRAM II, and QDRII+SRAM external memory interfaces.
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| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FC-FBGA |
| Package Description | Flip Chip Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 1020 |
| PCB | 1020 |
| Package Length (mm) | 33 |
| Package Width (mm) | 33 |
| Package Height (mm) | 3(Max) |
| Seated Plane Height (mm) | 3.5(Max) |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Family Name | Stratix® II |
| Maximum Number of User I/Os | 718 |
| RAM Bits | 2484.6Kbit |
| Device Logic Cells | 60440 |
| Process Technology | 90nm |
| Number of Multipliers | 144 (18x18) |
| Programmability | No |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Dedicated DSP | 36 |
| Speed Grade | 4 |
| Differential I/O Standards Supported | LVPECL|LVDS |
| Single-Ended I/O Standards Supported | LVTTL|CMOS|SSTL|HSTL |
| External Memory Interface | DDR SDRAM|DDR2 SDRAM|RLDRAM II|QDRII+SRAM |
| Device Number of DLLs/PLLs | 12 |
| Supported IP Core | Viterbi Compiler, High-Speed Parallel Decoder|RapidIO to AXI Bridge Controller (RAB)|PowerPC/SH/1960 System Controller|32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz |
| Supported IP Core Manufacture | Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc/PLDA |
| Total Number of Block RAM | 2+255+329 |
| Cage Code | 4BA62 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A001.a.7.a |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU |
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