Field Programmable Gate Array (FPGA) with 100,448 logic cells and 4.347 Mbit of RAM, built on 65nm process technology. Features 278 maximum user I/Os, 276 18x18 multipliers, and 4 DLLs/PLLs. Supports DDR2 SDRAM and QDRII+ SRAM external memory interfaces, along with a wide range of differential and single-ended I/O standards. Packaged in a 484-pin Fine Pitch Ball Grid Array (FBGA) for surface mounting, operating between 0°C and 85°C.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Intel EP3CLS100F484C8ES technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
484
PCB
484
Package Length (mm)
23
Package Width (mm)
23
Package Height (mm)
1.5
Seated Plane Height (mm)
2
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Jedec
MS-034AAJ-1
Family Name
Cyclone® III LS
Maximum Number of User I/Os
278
RAM Bits
4347Kbit
Device Logic Cells
100448
Process Technology
65nm
Number of Multipliers
276 (18x18)
Programmability
No
Program Memory Type
SRAM
Min Operating Temperature
0°C
Max Operating Temperature
85°C
Speed Grade
8
Differential I/O Standards Supported
LVPECL|LVDS|HSTL-18|HSTL-15|HSTL-12|SSTL-2|SSTL-18|RSDS
Single-Ended I/O Standards Supported
LVTTL|LVCMOS|PCI|PCI-X|SSTL|HSTL
External Memory Interface
DDR2 SDRAM|QDRII+SRAM
Device Number of DLLs/PLLs
4
Supported IP Core
Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Public Key Crypto Engine (BA414E)| 32|64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz
Supported IP Core Manufacture
Altera/CAST, Inc/Barco Silex/PLDA
Total Number of Block RAM
483
Compliance
Cage Code
4BA62
EU RoHS
No
HTS Code
8542390001
Schedule B
8542390000
ECCN
3A991.d
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Intel EP3CLS100F484C8ES Datasheet
Download the complete datasheet for Intel EP3CLS100F484C8ES to view detailed technical specifications.
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