Field Programmable Gate Array (FPGA) with 100,448 logic cells and 276 multipliers, operating at 437.5MHz with 65nm process technology. Features 483 total block RAM bits, 4.347 Mbit RAM bits, and 4 DLLs/PLLs. Supports up to 278 user I/Os with extensive differential and single-ended I/O standards, including DDR2 SDRAM and QDRII+ SRAM external memory interfaces. Housed in a 484-pin UFBGA package (19x19x1.5mm) for surface mounting.
PackageUFBGA
MountingSurface Mount
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Technical Specifications
Intel EP3CLS100U484C7N technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
UFBGA
Package Description
Ultra Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
484
PCB
484
Package Length (mm)
19
Package Width (mm)
19
Package Height (mm)
1.5
Seated Plane Height (mm)
1.9
Pin Pitch (mm)
0.8
Package Material
Plastic
Mounting
Surface Mount
Jedec
MO-275PPAA-2
Family Name
Cyclone® III LS
Maximum Number of User I/Os
278
RAM Bits
4347Kbit
Device Logic Cells
100448
Process Technology
65nm
Number of Multipliers
276 (18x18)
Programmability
No
Program Memory Type
SRAM
Min Operating Temperature
0°C
Max Operating Temperature
85°C
Speed Grade
7
Differential I/O Standards Supported
LVPECL|LVDS|HSTL-18|HSTL-15|HSTL-12|SSTL-2|SSTL-18|RSDS
Single-Ended I/O Standards Supported
LVTTL|LVCMOS|PCI|PCI-X|SSTL|HSTL
External Memory Interface
DDR2 SDRAM|QDRII+SRAM
Device Number of DLLs/PLLs
4
Supported IP Core
Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Public Key Crypto Engine (BA414E)| 32|64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz
Supported IP Core Manufacture
Altera/CAST, Inc/Barco Silex/PLDA
Total Number of Block RAM
483
Compliance
Cage Code
4BA62
EU RoHS
Yes
HTS Code
8542390001
Schedule B
8542390000
ECCN
3A991
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU
Datasheet
Intel EP3CLS100U484C7N Datasheet
Download the complete datasheet for Intel EP3CLS100U484C7N to view detailed technical specifications.
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