Field Programmable Gate Array (FPGA) with 198,464 logic cells and 413 user I/Os. Features 8019 Kbit RAM, 396 multipliers (18x18), and 891 total block RAM. Operates with 1.2V supply and utilizes 65nm process technology. Supports DDR2 SDRAM and QDRII+ SRAM external memory interfaces. Packaged in a 780-pin FBGA (Fine Pitch Ball Grid Array) with a 1mm pin pitch, suitable for surface mounting. Offers a wide range of differential and single-ended I/O standards.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Intel EP3CLS200F780I8N technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
780
PCB
780
Package Length (mm)
29
Package Width (mm)
29
Package Height (mm)
1.75
Seated Plane Height (mm)
2.25
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Jedec
MS-034AAM-1
Family Name
Cyclone® III LS
Maximum Number of User I/Os
413
RAM Bits
8019Kbit
Device Logic Cells
198464
Process Technology
65nm
Number of Multipliers
396 (18x18)
Programmability
No
Program Memory Type
SRAM
Min Operating Temperature
-40°C
Max Operating Temperature
100°C
Speed Grade
8
Differential I/O Standards Supported
LVPECL|LVDS|HSTL-18|HSTL-15|HSTL-12|SSTL-2|SSTL-18|RSDS
Single-Ended I/O Standards Supported
LVTTL|LVCMOS|PCI|PCI-X|SSTL|HSTL
External Memory Interface
DDR2 SDRAM|QDRII+SRAM
Device Number of DLLs/PLLs
4
Supported IP Core
Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Public Key Crypto Engine (BA414E)| 32|64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz
Supported IP Core Manufacture
Altera/CAST, Inc/Barco Silex/PLDA
Total Number of Block RAM
891
Compliance
Cage Code
4BA62
EU RoHS
Yes with Exemption
HTS Code
8542390001
Schedule B
8542390000
ECCN
3A991.d
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU
Datasheet
Intel EP3CLS200F780I8N Datasheet
Download the complete datasheet for Intel EP3CLS200F780I8N to view detailed technical specifications.
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