Field Programmable Gate Array (FPGA) with 70,208 logic cells and 200 18x18 multipliers, operating at 402MHz. This device utilizes 65nm process technology and features 2997 Kbit of RAM. It supports up to 278 user I/Os and offers external memory interfaces for DDR2 SDRAM and QDRII+ SRAM. The FPGA is housed in a 484-pin UFBGA package with a 0.8mm pin pitch, designed for surface mounting.
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Intel EP3CLS70U484C8N technical specifications.
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | UFBGA |
| Package Description | Ultra Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 484 |
| PCB | 484 |
| Package Length (mm) | 19 |
| Package Width (mm) | 19 |
| Package Height (mm) | 1.5 |
| Seated Plane Height (mm) | 1.9 |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MO-275PPAA-2 |
| Family Name | Cyclone® III LS |
| Maximum Number of User I/Os | 278 |
| RAM Bits | 2997Kbit |
| Device Logic Cells | 70208 |
| Process Technology | 65nm |
| Number of Multipliers | 200 (18x18) |
| Programmability | No |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Speed Grade | 8 |
| Differential I/O Standards Supported | LVPECL|LVDS|HSTL-18|HSTL-15|HSTL-12|SSTL-2|SSTL-18|RSDS |
| Single-Ended I/O Standards Supported | LVTTL|LVCMOS|PCI|PCI-X|SSTL|HSTL |
| External Memory Interface | DDR2 SDRAM|QDRII+SRAM |
| Device Number of DLLs/PLLs | 4 |
| Supported IP Core | Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Public Key Crypto Engine (BA414E)| 32|64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz |
| Supported IP Core Manufacture | Altera/CAST, Inc/Barco Silex/PLDA |
| Total Number of Block RAM | 333 |
| Cage Code | 4BA62 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A991 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU |
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