Field-Programmable Gate Array (FPGA) with 49,888 logic cells and 2502 Kbit RAM. Features 60nm process technology, 310 user I/Os, and 2 Ethernet MACs. Supports up to 3.125 Gbps transceiver speeds across 8 transceiver blocks. Includes 1 PCI block and 4 DLLs/PLLs. Packaged in a 672-pin FBGA (27x27mm) for surface mounting.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Intel EP4CGX50DF27C6ES technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
672
PCB
672
Package Length (mm)
27
Package Width (mm)
27
Package Height (mm)
1.75
Seated Plane Height (mm)
2.25
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Jedec
MS-034AAL-1
Family Name
Cyclone® IV GX
Maximum Number of User I/Os
310
RAM Bits
2502Kbit
Device Logic Cells
49888
Process Technology
60nm
Ethernet MACs
2
Number of Multipliers
140 (18x18)
Programmability
Yes
Transceiver Blocks
8
Transceiver Speed
3.125Gbps
Program Memory Type
SRAM
Min Operating Temperature
0°C
Max Operating Temperature
85°C
PCI Blocks
1
Speed Grade
6
Differential I/O Standards Supported
B-LVDS|HSTL|LVPECL|LVDS|RSDS|SSTL
Single-Ended I/O Standards Supported
LVTTL|LVCMOS|PCI|PCI-X|SSTL|HSTL
External Memory Interface
DDR2 SDRAM|QDRII+SRAM
Device Number of DLLs/PLLs
4
Supported IP Core
Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Sub-frame Latency JPEG 2000 Encoder (BA130)|PCI Express to AXI Bridge Controller (GPEX-PAB)|ISA/PC Card/PCMCIA/Compact Flash Host Adapter
Supported IP Core Manufacture
Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc
Total Number of Block RAM
278
Compliance
Cage Code
4BA62
EU RoHS
No
HTS Code
8542390001
Schedule B
8542390000
ECCN
3A991.d
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Intel EP4CGX50DF27C6ES Datasheet
Download the complete datasheet for Intel EP4CGX50DF27C6ES to view detailed technical specifications.
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