Complex Programmable Logic Device (CPLD) from the MAX® II family, featuring 1270 device logic cells and 980 macro cells. This surface-mount component utilizes 0.18um process technology and operates at clock speeds up to 201.1MHz. It supports dual operating voltages of 2.5V and 3.3V, with a minimum operating temperature of 0°C and a maximum of 85°C. The device is housed in a 144-pin Fine Pitch Ball Grid Array (FBGA) package, measuring 13mm x 13mm with a 1mm pin pitch.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Intel EPM1270F144C5NES technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
144
PCB
144
Package Length (mm)
13
Package Width (mm)
13
Package Height (mm)
1.8(Max)
Seated Plane Height (mm)
2.2(Max)
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Jedec
MO-192AAD-1
Family Name
MAX® II
Device Logic Cells
1270
Number of Logic Blocks/Elements
127
Number of Macro Cells
980
Program Memory Type
Flash
Process Technology
0.18um
Min Operating Temperature
0°C
Max Operating Temperature
85°C
Typical Operating Supply Voltage
2.5|3.3V
Min Operating Supply Voltage
2.375V
Programmability
Yes
In-System Programmability
Yes
Speed Grade
5
Compliance
Cage Code
4BA62
EU RoHS
Yes
HTS Code
8542390001
Schedule B
8542390000
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU
Datasheet
Intel EPM1270F144C5NES Datasheet
Download the complete datasheet for Intel EPM1270F144C5NES to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.