
Complex Programmable Logic Device (CPLD) from the MAX® II family, featuring 980 macro cells and 127 logic elements. This surface-mount component utilizes 0.18um process technology and operates at a maximum frequency of 247.5MHz. It offers 212 user I/Os and supports dual operating supply voltages of 2.5V and 3.3V. Packaged in a 256-pin Fine Pitch Ball Grid Array (FBGA) with a 17mm x 17mm footprint and 1mm pin pitch, it is designed for in-system programmability.
Intel EPM1270F256C4NES technical specifications.
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