Complex Programmable Logic Device (CPLD) featuring 1270 logic cells and 980 macro cells. This device operates at up to 304MHz, utilizing 0.18um process technology and a typical 1.8V supply voltage. It is housed in a 144-pin Fine Pitch Ball Grid Array (FBGA) package with a 1mm pin pitch, designed for surface mounting. The CPLD supports in-system programmability and operates within a temperature range of -40°C to 100°C.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Intel EPM1270GF144I3NES technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
144
PCB
144
Package Length (mm)
13
Package Width (mm)
13
Package Height (mm)
1.8(Max)
Seated Plane Height (mm)
2.2(Max)
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Jedec
MO-192AAD-1
Family Name
MAX® II
Device Logic Cells
1270
Number of Logic Blocks/Elements
127
Number of Macro Cells
980
Program Memory Type
Flash
Process Technology
0.18um
Min Operating Temperature
-40°C
Max Operating Temperature
100°C
Typical Operating Supply Voltage
1.8V
Min Operating Supply Voltage
1.71V
Programmability
Yes
In-System Programmability
Yes
Speed Grade
3
Compliance
Cage Code
4BA62
EU RoHS
Yes
HTS Code
8542390001
Schedule B
8542390000
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU
Datasheet
Intel EPM1270GF144I3NES Datasheet
Download the complete datasheet for Intel EPM1270GF144I3NES to view detailed technical specifications.
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