Complex Programmable Logic Device (CPLD) from the MAX® II family, featuring 1700 macro cells and 2210 device logic cells. This surface-mount component utilizes 0.18um process technology and operates at up to 304MHz with a typical supply voltage of 2.5V/3.3V. It offers 272 user I/Os and is housed in a 324-pin Fine Pitch Ball Grid Array (FBGA) package with a 1mm pin pitch. Designed for in-system programmability, it supports a temperature range of -40°C to 100°C.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Intel EPM2210F324I3NES technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 324 |
| PCB | 324 |
| Package Length (mm) | 19 |
| Package Width (mm) | 19 |
| Package Height (mm) | 1.25 |
| Seated Plane Height (mm) | 1.75 |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-034AAG-1 |
| Family Name | MAX® II |
| Device Logic Cells | 2210 |
| Number of User I/Os | 272 |
| Number of Logic Blocks/Elements | 221 |
| Number of Macro Cells | 1700 |
| Program Memory Type | Flash |
| Process Technology | 0.18um |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 100°C |
| Typical Operating Supply Voltage | 2.5|3.3V |
| Min Operating Supply Voltage | 2.375V |
| Programmability | Yes |
| In-System Programmability | Yes |
| Speed Grade | 3 |
Compliance
| Cage Code | 4BA62 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Intel EPM2210F324I3NES Datasheet
Download the complete datasheet for Intel EPM2210F324I3NES to view detailed technical specifications.
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